A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures-Reference-Cited by-同舟云学术

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A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures

Published:2012-06 Issue:2 Volume:2 Page:266-277
ISSN:2156-3357
Container-title:IEEE Journal on Emerging and Selected Topics in Circuits and Systems
language:
Short-container-title:IEEE J. Emerg. Sel. Topics Circuits Syst.

Author:

Nandakumar Vivek S.,Marek-Sadowska Malgorzata

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/5503868/6213508/06199999.pdf?arnumber=6199999

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An automated fault-tolerant route discovery with congestion control using TFRF model for 3D network-on-chips;International Journal of Communication Networks and Distributed Systems;2020

2. Analytical Modeling of Surface Potential and Threshold Voltage for Junctionless Double Gate Vertical Slit Field Effect Transistor;Journal of Nanoelectronics and Optoelectronics;2017-09-01

3. A 2D Potential Based Threshold Voltage Model Analysis and Comparison of Junctionless Symmetric Double Gate Vertical Slit Field Effect Transistor;IETE Journal of Research;2017-03-06

4. A survey of low power NoC design techniques;Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems;2017-01-25

5. High-speed reconfigurable card-to-card optical interconnects based on hybrid free-space and multi-mode fiber propagations;Optics Express;2013-12-10

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