A 60-Gb/s PAM4 Wireline Receiver with 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS-Reference-Cited by-同舟云学术

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A 60-Gb/s PAM4 Wireline Receiver with 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS

Published:2020-03 Issue: Volume: Page:
ISSN:
Container-title:2020 IEEE Custom Integrated Circuits Conference (CICC)
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Author:

Chen Kuan-Chang,Kuo William Wei-Ting,Emami Azita

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9060424/9075871/09075948.pdf?arnumber=9075948

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design Methods of Integrated Circuits, Working Under Non-standard Operating Conditions;Machine Learning-based Design and Optimization of High-Speed Circuits;2023-12-31

2. A 103 fJ/b/dB, 10–26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement;IEEE Journal of Solid-State Circuits;2023-10

3. A High-Speed Charge-Injection based Double Tail Latch for Decision Feedback Equalizer (DFE);2023 21st IEEE Interregional NEWCAS Conference (NEWCAS);2023-06-26

4. Research on Settling Time of Decision Feedback Equalizer;2022 10th International Symposium on Next-Generation Electronics (ISNE);2023-05-12

5. A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems;IEEE Journal of Solid-State Circuits;2022-05

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