A Front-End Channel in 65 nm CMOS for Pixel Detectors at the HL-LHC Experiment Upgrades

Author:

Ratti L.ORCID,De Canio F.,Gaioni L.,Manghisoni M.,Re V.,Traversi G.

Funder

CHIPIX65 experiment

Italian Institute for Nuclear Physics (INFN)

European Union’s Horizon 2020 Research and Innovation program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Nuclear Energy and Engineering,Nuclear and High Energy Physics

Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. CMOS readout FEE based TV-BLR module for CdZnTe pixel detectors in high count rate applications;Ain Shams Engineering Journal;2024-01

2. Von 65 nm bis 28 nm CMOS: Design analoger Bausteine von Frontend-Kanälen für Pixelsensoren in Hochenergiephysik-Experimenten;e & i Elektrotechnik und Informationstechnik;2023-12-29

3. Generic Analog 8 Bit DAC IP Block in 28nm CMOS for the High Energy Physics Community;2022 Austrochip Workshop on Microelectronics (Austrochip);2022-10-11

4. A Hybrid MT-ToT Design for CdZnTe/SiPM in Biomedical PET Applications;2022 International Conference on Computing, Electronics & Communications Engineering (iCCECE);2022-08-17

5. A PVT power immune compact 65 nm CMOS CSP design with a leakage current compensation feedback for CdZnTe/CdTe sensors dedicated to PET applications;International Journal of Circuit Theory and Applications;2022-03-04

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