Design of 20Gb/s PAM4 Transmitter with 2-tap FFE-Reference-Cited by-同舟云学术

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Design of 20Gb/s PAM4 Transmitter with 2-tap FFE

Published:2022-11-05 Issue: Volume: Page:
ISSN:
Container-title:2022 15th International Congress on Image and Signal Processing, BioMedical Engineering and Informatics (CISP-BMEI)
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Author:

Liu Xuena¹,Li Zhensong¹,Wen Hao¹,Miao Min¹

Affiliation:

1. Beijing Information Science and Technology University,Key Laboratory of Information and Communication Systems, Key Laboratory of the Ministry of Education for Optoelectronic Measurement Technology and Instrument, Ministry of Information Industry,Beijing,China,100101

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9979807/9979817/09980249.pdf?arnumber=9980249

Reference9 articles.

1. Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies

2. 42.8 Gbit/s PAM-4 data transmission over low-loss electrical backplane

3. A 50Gb/s low power PAM4SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology;lv;IEEE International Conference on ASIC,2016

4. A 40–80 Gb/s PAM4 wireline transmitter in 65nm CMOS technology

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