A power-efficient optimizing framework FPGA accelerator for YOLO
Author:
Affiliation:
1. School of artificial intelligence, Beijing Technology and Business University,Beijing,China
2. Research Institute,State Key Laboratory of Coal Mine Safety Technology, China Coal Technology and Engineering Group Shenyang,Shenyang,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9979807/9979817/09980321.pdf?arnumber=9980321
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1. Convolutional Neural Network Architecture for Geometric Matching
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1. Energy-Efficient Implementation of YOLOv8, Instance Segmentation, and Pose Detection on RISC-V SoC;IEEE Access;2024
2. A Low-Power Reconfigurable DNN Accelerator for Instruction-Extended RISC-V;IPSJ Transactions on System and LSI Design Methodology;2024
3. A Power-efficient end-to-end Implementation of YOLOv8 Based on RISC-V;2023 4th International Conference on Computers and Artificial Intelligence Technology (CAIT);2023-12-13
4. Sparsity Exploration for Structured and Unstructured Weight Formations in CNN Architecture;2023 Asia Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ASC);2023-10-31
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