A Framework for Mapping DRL Algorithms With Prioritized Replay Buffer Onto Heterogeneous Platforms
Author:
Affiliation:
1. Department of Computer Science, University of Southern California, Los Angeles, CA, USA
2. Department of Electrical and Computer Engineering, University of Southern California, Los Angeles, CA, USA
Funder
NSF
AMD Xilinx
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Computational Theory and Mathematics,Hardware and Architecture,Signal Processing
Link
https://ieeexplore.ieee.org/ielam/71/10123122/10093111-aam.pdf
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