A Parallel Algorithm to Accelerate DEVS Simulations in Shared Memory Architectures-Reference-Cited by-同舟云学术

A Parallel Algorithm to Accelerate DEVS Simulations in Shared Memory Architectures

Published:2023-05 Issue:5 Volume:34 Page:1609-1620
ISSN:1045-9219
Container-title:IEEE Transactions on Parallel and Distributed Systems
language:
Short-container-title:IEEE Trans. Parallel Distrib. Syst.

Author:

Trabes Guillermo German¹^ORCID,Wainer Gabriel A.²^ORCID,Gil-Costa Veronica³^ORCID

Affiliation:

1. Department of Systems and Computing Engineering, Carleton University, Ottawa, ON, Canada

2. Department of Systems and Computer Engineering, Carleton University, Ottawa, ON, Canada

3. National University of San Luis and CCT CONICET, San Luis, Argentina

Funder

NSERC Canada

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Signal Processing

Link

http://xplorestaging.ieee.org/ielx7/71/10075651/10068737.pdf?arnumber=10068737

Reference34 articles.

1. Performance analysis of real-time DEVS models

2. Efficient distributed simulation of hierarchical DEVS models: Transforming model structure into a non-hierarchical one;kim;Proc 33rd Annu Simul Symp,2000

3. hwloc: A Generic Framework for Managing Hardware Affinities in HPC Applications

4. Complexity Analysis on Flattened PDEVS Simulations

5. Definition of real-time simulation in the CD++ toolkit;glinsky;Proc Summer Comput Simul Conf,2002

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