HPC Hardware Design Reliability Benchmarking With HDFIT
Author:
Affiliation:
1. Intel Corporation, Santa Clara, CA, USA
2. Department of Informatics, Technical University Munich, Munich, Germany
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Computational Theory and Mathematics,Hardware and Architecture,Signal Processing
Link
http://xplorestaging.ieee.org/ielx7/71/10012125/10018868.pdf?arnumber=10018868
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