A novel design method for SOGI-PLL for minimum settling time and low unit vector distortion-Reference-Cited by-同舟云学术

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A novel design method for SOGI-PLL for minimum settling time and low unit vector distortion

Published:2013-11 Issue: Volume: Page:
ISSN:
Container-title:IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society
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Author:

Kulkarni Abhijit,John Vinod

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6683943/6699103/06699148.pdf?arnumber=6699148

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