Design, Implementation, and Power Analysis for Network-on-Chip Architectures-Reference-Cited by-同舟云学术

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Design, Implementation, and Power Analysis for Network-on-Chip Architectures

Published:2023-05-10 Issue: Volume: Page:
ISSN:
Container-title:2023 7th International Multi-Topic ICT Conference (IMTIC)
language:
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Author:

Farman Ayesha¹,Durrani Yaseer Arafat¹

Affiliation:

1. UET Taxila University of Engineering and Technology Taxila,Department of Electronics Engineering,Taxila,Pakistan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10178421/10178434/10178545.pdf?arnumber=10178545

Reference20 articles.

1. Power Analysis of 2D Torus on chip;r e;Journal of Low Power Electronics,2010

2. Power analysis and optimization of Torus based on NOC;s;IEEE Trans Comput -Aided Design Integrated Circ Syst,2014

3. A power efficient router for 2D torus based NOCs;kim;IEEE Trans on Computers 2012,2012

4. Power Analysis and Optimization;Vivado Design Suite User,2012

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