Speed-Up Gate Pulse Method to Suppress Switching Loss and Surge Voltage for MOS Gate Power Devices
Author:
Affiliation:
1. Kyushu Institute of Technology,Next Generation Power Electronics Research Center,Kitakyushu,Japan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9813543/9813532/09813653.pdf?arnumber=9813653
Reference8 articles.
1. Stop-and-Go Gate Drive Minimizing Test Cost to Find Optimum Gate Driving Vectors in Digital Gate Drivers
2. General-purpose clocked gate driver (CGD) IC with programmable 63-level drivability to reduce Ic overshoot and switching loss of various power transistors
3. Digital Active Gate Drive with Optimal Switching Patterns to Adapt to Sinusoidal Output Current in a Full Bridge Inverter Circuit
4. Benchmarking of Digital Gate Driven IGBTs: New Eoff-Vsurge Trade-off Approach
5. Active Gate Control in Half-Bridge Inverters Using Programmable Gate Driver ICs to Improve Both Surge Voltage and Converter Efficiency
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