A Reconfigurable Bit-Serial VLSI Systolic Array Neuro-Chip-Reference-Cited by-同舟云学术

A Reconfigurable Bit-Serial VLSI Systolic Array Neuro-Chip

Published:1997-07 Issue:1 Volume:44 Page:53-70
ISSN:0743-7315
Container-title:Journal of Parallel and Distributed Computing
language:en
Short-container-title:Journal of Parallel and Distributed Computing

Author:

Murtagh Paul J.,Tsoi Ah Chung

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software

Reference36 articles.

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3. A. Candaten, 1994, Development and implementation of NOL: A neural object language, University of Queensland

4. A taxonomy of reconfigurable techniques for fault-tolerant processor arrays;Chean;Computer,1990

5. VLSI Signal Processing: A Bit-Serial Approach;Denyer,1985

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