1. P. H. Langade, and S.B. Patil, “A Survey on Systolic Array Multiplier and its Implementation on FPGA,” vol. 4, no. 5, pp. 1299 - 1302, 2015.
2. J.H. Weston, C.N. Zhang and Hua Li, “Some Space Considerations of VLSI Systolic Array Mappings,” IEEE, pp. 375-381, 2000.
3. L. D Whitley, A. E. Howe, S. Rana, J.P. Watson, L. Barbulescu, “Comparing Heuristic Search Methods and Genetic Algorithms for Warehouse Scheduling,” In SMC'98 Conference Proceedings, IEEE International Confer- ence on Systems, Man, and Cybernetics, vol. 3, pp. 2430 – 243, 1998.
4. Poonam Garg, “A comparison between Memetic algorithm and Genetic Algorithm for the cryptanalysis of simplified Data Encryption Standard Algorithm,” International Journal of Network Security and Its Applications, vol. 1, no. 1, pp. 34 – 42, 2009.
5. E. Garca-Gonzalo, J. L. Fernndez-Martnez, “A Brief Historical Review of Particle Swarm Optimization (PSO),” Journal of Bioinformatics and Intelligent Control, Vol. 1, pp.3-16, 2012.