Diagnostics of semiconductor structures by electrochemical capacitance-voltage profiling technique

Abstract

The properties of interfaces in the heterostructures which frequently govern their operation are of particular importance for the devices containing heterostructures as active elements. Any further improving of the characteristics of semiconductor devices is impossible without a detail analysis of the processes occurring at the interfaces of heterojunctions. At the same time, the results largely depend on the purity of the starting materials and the technology of layer manufacturing. Moreover, the requirements to the composition and distribution of the impurity steadily get stringent. Therefore, the requirements regarding the methods of the impurity control and carrier distribution also become tougher both in the stage of laboratory development of the structure and in various stages of manufacturing of semiconductor devices. Electrochemical capacitance-voltage profiling is distinguished among the methods of electrical diagnostics of semiconductors by the absence of special preparation of the structures and deposition of the contacts to perform measurements, thus providing for gaining information not only about the impurity distribution but also about the distribution of free carriers. The goal of this work is to perform precise measurements of the profiles of free carrier distribution in semiconductor structures of different types, and demonstrate the measuring capabilities of a modern technique for concentration distribution diagnostics, i.e., electrochemical capacitance-voltage profiling. The method allows verification of the layer thickness in semiconductor heterostructures and provide a useful and informative feedback to technologists. To increase the resolution of the method and broad up the range of available test frequencies, a standard electrochemical profiler has been modified. Mapping data for GaAs substrate structure, the profiles of the concentration distribution of the majority charge carriers in SiC structures, GaAs structure with a p – n junction, pHEMT heterostructure, GaN heterostructure with multiple quantum wells, and in a silicon-based solar cell heterostructure are presented. The obtained results can be used to analyze the physical properties and phenomena in semiconductor devices with quantum-sized layers, as well as to improve and refine the parameters of existing electronic devices.