Threshold Inverter Quantizer-Based 2-Bit Comparator using Spatial Wavefunction Switched (SWS) FET Inverters: Power Dissipation Analysis

Abstract

This paper aims to assess the power dissipation of a threshold quantizer (TIQ) 2-bit-based comparator using a SWS-FET-based inverter [ 1 , 2 , 4 , 5 ]. Unlike conventional comparators, SWS-based comparator functionalized with TIQ comprises two or more vertically stacked quantum dots or well channels [ 1 – 3 , 5 , 6 ]. Herein, power dissipation analysis of the simulated circuit is carried out using Cadence by integrating the Berkeley Short-Channel IGFET Model (BSIM) and the analog behavioral model (ABM) [ 1 , 3 , 4 , 9 ]. The transient behavior of the inverter circuit is evaluated using 180[Formula: see text]nm technology node. Our results demonstrated a significant reduction in power dissipation which overcome the limitation of previous 4-state logic implementations.