Parallel Architecture of Reconfigurable Hardware for Massive Output Active Noise Control

Abstract

Filtered-x Least Mean Squares (FxLMS) is an algorithm commonly used for Active Noise Control (ANC) systems in order to cancel undesired acoustic waves from a sound source. There is a small number of hardware designs reported in the literature, that in turn only use one reference signal, one error signal and one output control signal. In this paper, it is proposed a 3-dimensional hardware-based version of the widely used FxLMS algorithm, using one reference microphone, 18 error microphones, one output and a FIR filter of 400[Formula: see text] order. The FxLMS algorithm was implemented in a Xilinx Artix 7 FPGA running at 25 MHz, which allowed to update the filter coefficients in 32.44[Formula: see text] s. The main idea behind this work is to propose a pipelined parallelized architecture to achieve processing times faster than real time for the filter coefficients update. The main contribution of this work is not the ANC technique itself, but rather the proposed hardware implementation that utilizes integer arithmetic, which provided an acceptable error when benchmarked with a software implementation. This parallel system allows a scalable implementation as an advantage of using FPGA without compromising the computational cost and, consequently, the latency.