AUTOMATED DEBUGGING OF VERILOG DESIGNS
Author:
Affiliation:
1. Softnet Austria, Inffelgasse 16b/II, 8010 Graz, Austria
2. Shaheed Zulfikar Ali Bhutto Institute of Science and Technology, 44000 Islamabad, Pakistan
3. Institute for Software Technology, Technische Universität Graz, 8010 Graz, Austria
Abstract
Publisher
World Scientific Pub Co Pte Lt
Subject
Artificial Intelligence,Computer Graphics and Computer-Aided Design,Computer Networks and Communications,Software
Link
https://www.worldscientific.com/doi/pdf/10.1142/S0218194012500209
Reference13 articles.
1. Relating Event and Trace Semantics of Hardware Description Languages
2. A theory of diagnosis from first principles
3. Model-based diagnosis of hardware designs
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