AUTOMATED DEBUGGING OF VERILOG DESIGNS

Author:

PEISCHL BERNHARD1,RIAZ NAVEED2,WOTAWA FRANZ3

Affiliation:

1. Softnet Austria, Inffelgasse 16b/II, 8010 Graz, Austria

2. Shaheed Zulfikar Ali Bhutto Institute of Science and Technology, 44000 Islamabad, Pakistan

3. Institute for Software Technology, Technische Universität Graz, 8010 Graz, Austria

Abstract

In this article we report on novel insights in model-based software debugging of hardware description languages (HDLs). Today's simulation driven working process emphasizes the need for exploiting test suites not only for detecting but also for localizing the root cause of misbehavior. We discuss the modeling approaches for the various artifacts of the Verilog hardware description language (blocking and non-blocking statements, expressions, execution ordering) and present a novel model incorporating test suites. The evaluation of our approach on the well-known ISCAS89 benchmarks concerning single and double-fault diagnoses clearly indicates that incorporating test suites into the fault localization technique (and development process) considerably improves the accuracy of the obtained diagnosis candidates.

Publisher

World Scientific Pub Co Pte Lt

Subject

Artificial Intelligence,Computer Graphics and Computer-Aided Design,Computer Networks and Communications,Software

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Time-Aware Spectrum-Based Bug Localization for Hardware Design Code with Data Purification;ACM Transactions on Architecture and Code Optimization;2024-09-14

2. Model-Driven Intelligent Decision Support Systems;Intelligent Decision Support Systems;2022

3. Fault localization based on statement frequency;Information Sciences;2016-09

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