CLOCK JITTER EFFECT ON SWITCHED-CAPACITOR FILTER DESIGN

Abstract

This paper proposes the study of clock jitter effect on high-Q switched-capacitor filter behavior. A command circuit made up by a ring voltage controlled oscillator (VCO) with XOR gates is used to generate the command signals. According to the correlation of these signals the jitter effect on the signal constellation has been studied. A good agreement between measured and simulation results has been achieved which validate our design methodology.