Low Power Static Random-Access Memory Cell Design for Mobile Opportunistic Networks Sensor Nodes

Abstract

In the present scenario, the devices supporting neighbor discovery are going through the renovation phase, and crossing the classical barrier such as the trade-off between power dissipation and access time. The presence of opportunistic nodes in place of static nodes has presented multiple challenges for such devices. Therefore, the focus of neighbor discovery has mostly shifted toward such issues where power dissipation and latency of mobile nodes need to be simultaneously improved to achieve uninterrupted and quality communication. Since static random-access memory (SRAM) is an integral part of all such sensor nodes and directly impacts power dissipation and latency, therefore in this paper, we have introduced a novel SRAM cell for such nodes. The proposed eleven transistors (11T) SRAM cell is compared with six recently reported designs to check the improvement of SRAM key design parameters. The compared designs include Standard 6T (S6T), tunable 8T(TU8T), PPN-based 10T (PN10T), Schmitt trigger-based 10T (S10T), bit-line-dependent 11T (DP11T) bit-cell and stable low power 11T (SP11T). The improvement in write ability and read stability of proposed 11T cell is represented by [Formula: see text] and [Formula: see text] enhancement of write and read static margins, respectively, in comparison to S6T/TU8T/PN10T/S10T/DP11T/SP11T. Further, the leakage power dissipation is reduced by [Formula: see text] as compared to S6T/TU8T/S10T/PN10T/DP 11T/SP11T. Additionally, power dissipation and delay of proposed 11T cell during read operation is reduced by [Formula: see text] and [Formula: see text], respectively, as compared to S6T/TU8T/PN10T/S10T/DP11T/SP11T. It is worth mentioning here that the proposed 11T also shows narrower variability in power dissipation and current values during read operation comparing S6T. The proposed 11T design successfully mitigates the half-select issue and allows the SRAM array to attain the bit-interleaved architecture implementation.