DIGITAL BACKGROUND CALIBRATION FOR TIMING SKEW IN TIME-INTERLEAVED ADC-Reference-Cited by-同舟云学术

DIGITAL BACKGROUND CALIBRATION FOR TIMING SKEW IN TIME-INTERLEAVED ADC

Published:2014-06-18 Issue:08 Volume:23 Page:1450117
ISSN:0218-1266
Container-title:Journal of Circuits, Systems and Computers
language:en
Short-container-title:J CIRCUIT SYST COMP

Author:

LI JING¹,LIU YANG¹,WU SHUANGYI¹,NING NING¹,YU QI¹

Affiliation:

1. State Key Lab of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Room 1003, Building 211, No. 4, Section 2, North Jianshe Road, Chengdu 610054, P. R. China

Abstract

This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). The timing error is detected by using the first derivative of the channel ADCs and a least-mean-square (LMS) loop is exploited to compensate the timing skew. The proposed scheme is effective within the entire frequency range of 0–fs/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes lesser power and smaller area.

Publisher

World Scientific Pub Co Pte Lt

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

Link

https://www.worldscientific.com/doi/pdf/10.1142/S0218126614501175

Reference6 articles.

1. A 12-Bit 3 GS/s Pipeline ADC With 0.4 mm$^{2}$ and 500 mW in 40 nm Digital CMOS

2. A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS

3. A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration

4. A Four-Channel Time-Interleaved ADC With Digital Calibration of Interchannel Timing and Memory Errors

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