An Analytical GPU-Enabled Framework for the Stacked 3D IC Layouts

Abstract

Three-dimensional integrated circuits (3D ICs) have recently garnered significant attention as a potential solution to the challenges posed by interconnect scaling in 2D ICs. However, the inclusion of an extra dimension and the introduction of through-silicon vias (TSVs) for interlayer connections have resulted in a significantly more complex compared to traditional 2D placement. In this paper, we propose an analytical framework for the stacked 3D ICs. Specifically, our approach involves the diffusion of standard and macro modules in the presence of wirelength and density forces, followed by a 2D mixed-size placement to optimize placement. To eliminate the overlap between macros, we perform legalization and fix them. The TSV insertions are then conducted, and we fix them in the center of the 3D net. Finally, legalization and detailed placement for cells are performed layer-by-layer. Furthermore, to improve the efficiency of the proposed framework, we propose a GPU-enabled acceleration strategy that accelerates the wirelength computation based on the deep learning toolkit PyTorch. Extensive experimental results on the standard-cell IBM-PLACE benchmarks and large-scale modern mixed-size (MMS) benchmarks demonstrate that the proposed framework outperforms state-of-the-art 3D placement methods.