EnCache: A DYNAMIC PROFILING-BASED RECONFIGURATION TECHNIQUE FOR IMPROVING CACHE ENERGY EFFICIENCY

Author:

MITTAL SPARSH1,ZHANG ZHAO2

Affiliation:

1. Future Technologies Group, Oak Ridge National Laboratory (ORNL), Oak Ridge, Tennessee 37830, United States

2. Department of Electrical and Computer Engineering, Iowa State University, Ames, Iowa 50014, United States

Abstract

With each CMOS technology generation, leakage energy consumption has been dramatically increasing and hence, managing leakage power consumption of large last-level caches (LLCs) has become a critical issue in modern processor design. In this paper, we present EnCache, a novel software-based technique which uses dynamic profiling-based cache reconfiguration for saving cache leakage energy. EnCache uses a simple hardware component called profiling cache, which dynamically predicts energy efficiency of an application for 32 possible cache configurations. Using these estimates, system software reconfigures the cache to the most energy efficient configuration. EnCache uses dynamic cache reconfiguration and hence, it does not require offline profiling or tuning the parameter for each application. Furthermore, EnCache optimizes directly for the overall memory subsystem (LLC and main memory) energy efficiency instead of the LLC energy efficiency alone. The experiments performed with an ×86-64 simulator and workloads from SPEC2006 suite confirm that EnCache provides larger energy saving than a conventional energy saving scheme. For single core and dual-core system configurations, the average savings in memory subsystem energy over a shared baseline configuration are 30.0% and 27.3%, respectively.

Publisher

World Scientific Pub Co Pte Lt

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Conflict-Aware Capacity Control Mechanism for Deep Cache Hierarchy;IEICE Transactions on Information and Systems;2022-06-01

2. A Survey Of Techniques for Architecting DRAM Caches;IEEE Transactions on Parallel and Distributed Systems;2016-06-01

3. A Survey of Cache Bypassing Techniques;Journal of Low Power Electronics and Applications;2016-04-28

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