Kapees3: A High-Quality VLSI Placement Tool Using Nesterov’s Method for Density Penalty

Author:

Pawanekar Sameer1ORCID,Kapoor Kalpesh2,Trivedi Gaurav1

Affiliation:

1. Department of Electronics and Electrical Engineering, Indian Institute of Technology Guwahati, India

2. Department of Mathematics, Indian Institute of Technology Guwahati, India

Abstract

We present an analytical approach that is based on nonlinear programming to perform VLSI standard cell placement. Our method first clusters a netlist to reduce the number of cells and then performs quadratic optimization on the reduced netlist. Finally, it uses Nesterov’s method for solving nonlinear equations for the problem. The framework of our tool, Kapees3, is scalable and generates high quality results. The experimental results for Peko Suite 1 and Peko Suite 2 benchmarks show promising improvements. Our placement tool outperforms NTUPlace3, Dragon, Feng Shui, Capo10.5, by 46%, 57%, 48% and 25%, respectively, on PEKO Suite 1. For PEKO Suite 2, our placement tool outperforms NTUPlace3, Dragon, Feng Shui, Capo10.5 and mPL6 by 30%, 47%, 57%, 69% and 2.7%, respectively. On MMS benchmarks, we obtain wirelength improvement over Capo10.5 by 56.62%, FLOP by 7.84%, FastPlace by 11.55%, ComPLx by 4.58%, POLAR by 23.67%, mPL6 by 9.96% and NTUPlace3-Unified by 2.96%.

Publisher

World Scientific Pub Co Pte Lt

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

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