A Low-Voltage Two-Stage Enhanced Gain Bulk-Driven Floating Gate OTA

Abstract

This paper presents a two-stage enhanced gain bulk-driven floating gate OTA (EG-BDFG OTA) using flipped voltage follower (FVF). The gain of the OTA is increased with the help of a self-biased summing stage followed by a conventional common-source stage. To ensure the stability of the proposed two-stage OTA, cascode compensation technique is used. The circuit is designed and simulated in Cadence Virtuoso tool using UMC 0.18-[Formula: see text]m CMOS technology library. The simulation results indicate that the proposed design has an improved voltage gain of 59[Formula: see text]dB that is 3.5 times more than that of the single-stage BDFG-FVF OTA. The linearity of the proposed OTA is almost maintained while enhancing the gain by 42[Formula: see text]dB. The circuit delivers [Formula: see text]65[Formula: see text]dB of HD3 and [Formula: see text]56[Formula: see text]dB of THD when a 0.2-Vpp differential input signal of 1-MHz frequency is applied. The circuit is also verified for process variations at different corners with the aid of Monte Carlo and Corner analyses. The layout of the proposed EG-BDFG OTA is also drawn and presented in the paper.