0.4-V Bulk Driven Logarithmic Amplifier for Ultra-Low-Power Biomedical Applications

Abstract

This paper presents a design and simulation of a low-noise, low-voltage, and low-power complementary metal oxide semiconductor (CMOS) logarithmic amplifier for biomedical applications like digital hearing aid applications. The amplifier block of analog front end is used as a logarithmic amplifier, based on the progressive-compression parallel-summation architecture with DC offset cancelation by adding an off-chip coupling capacitor at each stage. A fully nontailed differential limiting amplifier with bulk-driven input pair is used to achieve larger voltage gain and low voltage operation. The proposed logarithmic amplifier was designed and simulated with process parameters variation in standard 0.18-[Formula: see text]m CMOS technology. The circuit operates with a single 0.4-V power supply voltage and dissipates 0.832[Formula: see text][Formula: see text]W. The simulated input dynamic range is about 60[Formula: see text]dB, which covers the input amplitudes ranging from 1[Formula: see text][Formula: see text]V to 10[Formula: see text]mV, and the [Formula: see text]3-dB bandwidth of the amplifier is from 400[Formula: see text]Hz to 8.27[Formula: see text]kHz with simulated total input-referred noise is 0.731[Formula: see text][Formula: see text]V@8 kHz.