Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on Robust C-Elements

Abstract

Glitch at the input can increase the power consumption of flip-flop greatly. To solve this problem effectively, a Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on Robust C-Elements (LARC) is proposed in this paper. The proposed Latch Multiplexer-A Double-edge Triggered Flip-flop (LARC-DET) can effectively block the glitch at the input and prevent the redundant transition at internal nodes. As a result, the extra power consumption caused by the glitch at the input is effectively reduced. The simulation was performed using HSPICE under 32[Formula: see text]nm complementary metal oxide semiconductor (CMOS) process. The simulation results show that, compared with 12 double edge flip-flops, the proposed LARC-DET is the lowest in terms of power consumption and power delay product. Process voltage temperature (PVT) variation analysis shows its insensitivity to voltage variation, temperature variation and process variation.