FPGA Implementation of the Generalized Parallel Two-Box Model-based Digital Predistorter for Wireless Transmitters

Abstract

In this paper, the FPGA implementation of the generalized parallel two-box (GPTB) model is proposed. The blocks such as multipliers, complex magnitude calculator, and magnitude powers calculator have been utilized to implement the GPTB model. In the implementation of the proposed model, a total of 30 complex multipliers, 56 noncomplex multipliers and 56 adders were used. The GPTB DPD model has been implemented by using System Generator and Vivado software. The FPGA with a part number of xc7vx690t-3 from Xilinx has been employed to implement the model. The simulation results demonstrate the correctness of the implemented model in Vivado. Also, the verification of the GPTB model is accomplished by means of the simulation of the transmitter excited by QAM signals in the ADS software. The measure of an adjacent channel power ratio (ACPR) decreased by about 16[Formula: see text]dB as a result of the simulation.