Microprocessor Testing: Functional Meets Structural Test

Author:

Touati A.1,Bosio A.1,Girard P.1,Virazel A.1,Bernardi P.2,Sonza Reorda M.2

Affiliation:

1. LIRMM - UM/CNRS, 161, rue Ada, 34095 Montpellier, France

2. Politecnico di Torino, Corso Duca degli Abruzzi, 24, 10129 Torino, Italia

Abstract

Structural test is widely adopted to ensure high quality for a given product. The availability of many commercial tools and the use of fault models make it very easy to generate and to evaluate. Despite its efficiency, structural test is also known for the risk of over-testing that may lead to yield loss. This problem is mainly due to the fact that structural test does not take into account the functionality of the circuit under test. On the other hand, functional test guarantees that the circuit is tested under normal conditions, thus avoiding any over- as well as under-testing issues. More in particular, for microprocessor testing, functional test is usually applied by exploiting the Software-Based-Self-Test (SBST) technique. SBST applies a set of functional test programs that are executed by the processor to achieve a given fault coverage. SBST fits particularly well for online testing of processor-based systems. In this work, we describe a technique able to execute functional test programs as if they were structural tests. In this way, they can be applied during the end-of-production test in order to achieve good fault coverage and, at the same time, avoiding any over-test problems. We will show that it is possible to map functional test programs into the classical structural test schemes, so that their application simply requires the presence of a scan chain. Finally, we present a compaction algorithm able to significantly reduce the test length. Results carried out on two different microprocessors show the advantages of such approach.

Publisher

World Scientific Pub Co Pte Lt

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Black-Box Test-Cost Reduction Based on Bayesian Network Models;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021-02

2. Software-Based Self-Test for Transition Faults: a Case Study;2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC);2019-10

3. HASTI: hardware‐assisted functional testing of embedded processors in idle times;IET Computers & Digital Techniques;2019-01-18

4. Exploring System Availability During Software-Based Self-Testing of Multi-core CPUs;Journal of Electronic Testing;2018-01-27

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