A Technique to Determine the Designable Inductance Value(s) in Wide-Band CMOS-Amplifier System Employing Shunt-Peaking

Abstract

This paper presents a technique towards obtaining an estimate of the value of inductor(s) to expand the bandwidth of operation in a complementary metal-oxide semiconductor (CMOS) amplifier system which exploits shunt peaking principle. The basic principle is placement of the zeros of the transfer function in an interleaved manner relative to the uncompensated RC time-constant frequency (TCF) and the band-edge frequency (BEF) (i.e., product of the poles) of the transfer function. Application of the analytical results has been demonstrated for (i) a common-gate (CG) amplifier stage in a 0.18-μm CMOS process and (ii) an inter-stage inductor coupling network which serves as an interface between two amplifier stages. MATLAB simulation has been used to obtain the range of design inductance values. The TSMC 180-nm CMOS process has been used in Cadence CAD environment to validate the theoretical predictions. The inductors laid out have been modeled using the ASITIC program to obtain more realistic results. The proposed technique provides a bandwidth extension of the CMOS common-gate amplifier from 6.68 GHz to 10.4 GHz with 1 dB peaking using only a 1.85-nH inductor. For the inter-stage coupling network, the suggested design procedure leads to a bandwidth extension ratio (BWER) exceeding three, with less than 3-dB ripple.