Implementation Guidelines of WDSRAM and Comparison with Typical SRAM Using Nanoscale Hierarchical Implementation Model

Abstract

In this work, we extend the implementation guidelines of the WDSRAM — Write Driver SRAM — through the definition of a hierarchical implementation model which is applied on the material layout memory design level. This model can be used in order to create WDSRAMs of any size, maintaining the memory’s write function speed-up against the typical SRAM implementation model. The post-layout simulation results are presented in comparison with the corresponding results of the typical SRAM and confirm that the WDSRAM write function speed-up is maintained against the typical SRAM when the memory size increases. A brief background knowledge on the WDSRAM function is also provided.