A NOVEL ALLOCATION METHODOLOGY FOR PARTIAL AND DYNAMIC BITSTREAM GENERATION FOR FPGA ARCHITECTURES

Abstract

Partial re-configuration is the process of configuring a portion of a FPGA while the rest of the device is still running/operating. This paper proposes a novel allocation methodology for realizing applications with partial and dynamic features on FPGAs. The methodology was implemented as a manager that incorporates two stages: the first one modifies the configuration data of each partial bitstream by replacing the associated application's functionalities (or slices), its goal being to compact the slice distribution, while keeping the same functionality. The second one determines the appropriate spatial location over the FPGA device where the previously optimized configuration data should be placed. The proposed manager is device independent, since it derives partial configuration data that can program dynamically any island-style or hierarchical FPGA. For demonstration purposes, the proposed manager was implemented as part of an existing bitstream generator tool, named DAGGER (part from the MEANDER framework) targeting to Virtex-like architectures.