Neural Network-Based Entropy: A New Metric for Evaluating Side-Channel Attacks

Author:

Cheng Jiafeng1,Sun Nengyuan1,Liu Wenrui1,Peng Zhaokang1,Wang Chunyang1,Sun Caiban1,Wang Yufei1,Bi Yijian1,Wen Yiming1,Zhang Hongliu2,Zhang Pengcheng2,Kose Selcuk3,Yu Weize1ORCID

Affiliation:

1. School of Microelectronics, Shandong University, Jinan, Shandong 250101, P. R. China

2. TIH Microelectronics Limited Corporation, Jinan, Shandong 250101, P. R. China

3. Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY 14627, USA

Abstract

Side-channel attacks (SCAs) are powerful noninvasive attacks that can be used for leaking the secret key of integrated circuits (ICs). Numerous countermeasures were proposed to elevate the security level of ICs against SCAs. Unfortunately, it is quite inconvenient to predict the security levels of these countermeasures since no solid mathematical model exists in the literature. In this paper, neural network (NN)-based entropy is proposed to model the resilience of a system against SCAs. The NN-based entropy model well links the side-channel leakages and probabilities with the neurons and weights of NNs, respectively. In such a circumstance, the NN-based entropy can be used for modeling the robustness of countermeasures since a one-to-one relationship is established between the NN-based entropy and the measurement-to-disclose (MTD) enhancement ratio related with the countermeasures. As demonstrated in the result, the proposed NN-based entropy metric shows 100% consistency with the MTD enhancement ratio if multiple SCA countermeasures are employed into a system.

Funder

Shandong University Qilu Young Scholar Program

Key Research and Development Project of Shandong Province

Publisher

World Scientific Pub Co Pte Ltd

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Media Technology

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A 128-Gbps Pipelined SM4 Circuit With Dual DPA Attack Countermeasures;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-06

2. A novel SM4 cryptographic architecture against higher order power analysis attacks;International Journal of Circuit Theory and Applications;2024-01-31

3. A high‐speed and low‐latency hardware implementation of RC4 cryptographic algorithm;International Journal of Circuit Theory and Applications;2023-08-15

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