A Carry Chain-Based ADMFC Design on an FPGA for EMI Reduction and Noise Compensation

Abstract

An all-digital multi-frequency clocking (ADMFC) circuit is proposed to reduce electromagnetic interference (EMI) on a field-programmable gate array (FPGA) architecture, while supporting dynamic adaptation to voltage noises. The proposed ADMFC uses dedicated high-speed carry chain paths in an FPGA to finely adjust the clock frequency by controlling the number of carry propagations on the carry chain logics (CARRY4 cells) in the delay line of a ring oscillator. Moreover, supply voltage variation and noise caused by circuit switchings can be compensated by dynamically adjusting the length of ripple carry propagations on the cascaded CARRY4 cells in response to the detected voltage variation. Finally, a selectable modulation profile is devised to provide a much suitable profile between two different profiles at run-time for the given noise constraints and working environment of a chip. Measurement results show that at the frequency of 44.6[Formula: see text]MHz, the ADMFC can obtain 17[Formula: see text]dB and 19.4[Formula: see text]dB EMI attenuations with a 7.5% spreading ratio when using triangular and sawtooth profiles, respectively. The proposed ADMFC is suitable for applications such as biological sensor nodes or IoT related systems which typically operate at a low-frequency band.