MONOTONIC ERROR ELIMINATION IN SUBRANGE A/D CONVERTERS

Abstract

Monotonic errors cause severe errors and are inherent in several A/D Converter (ADC) architectures. Moreover, several error correcting and ADC output processing methods require a monotonic behavior for a successful operation. Based on the features of asynchronous ADCs, an architecture for the elimination of monotonic errors is presented. This monotonic error correcting module is connected at the output of an ADC and does not require any modification in its internal circuits. It controls an output buffering stage that discards output codes with monotonic errors and this correcting procedure is triggered by changes in specific output bits of the ADC. Simulation results show an improvement by 8 dB or 25% maximum, in the signal-to-noise and distortion ratio (SNDR) of an 8-bit ADC if this monotonic error elimination method is used alone and a further improvement by 1–5 dB if it is combined with a post processing method developed by the authors. Similar improvement can also be achieved in several other architectures like Subrange or Folding ADCs that operate in relatively high oversampling ratio and suffer from monotonic errors with specific features.