Electrical Characterization of the Clamping Behavior on CMOS Quasi-Floating-Gate Circuits

Abstract

In this paper, the clamping effect introduced by several diode-based configurations used for the implementation of the high-value resistors in quasi-floating-gate circuits is analyzed and characterized. In contrast to previous approaches where a parasitic diode is treated as a simple high-value resistor reducing the circuit complexity, in this case the analysis considers the diode behavior which leads to a clamping circuit. This clamping circuit introduces an unwanted amplitude-dependent offset voltage, which affects the performance moving the quiescent point at the quasi-floating-gate transistors. A new anti-parallel diode configuration for quasi-floating-gate applications is proposed in this work, which eliminates this unwanted offset voltage. The proposed design is validated using simulations and experimental data in a CMOS 0.35-[Formula: see text]m technology.