A New Tunable SISO Filter Designed in 40nm CMOS for Bilateral Inverse and Buffer Filtering Applications

Abstract

A new study imitating the design and implementation of single-input–single-output (SISO) filters as bilateral filters has been presented in this paper. Second generation current controlled current conveyor (CCCII), being a popular low power active element was considered for the realization of the proposed design. Complete design, analysis and implementation of the voltage mode SISO filter was done using only two CCCII’s and two passive parasitic components. The striking feature of this work is that the proposed design can be made to work at either the input node or the output node, as well as in the cases; the change of direction changes the filter into an inverse filter and buffer filter. Basic filter applications like low-pass, high-pass, band-pass and band-stop were aimed to check the uniformity of the proposed design at different frequencies. Results perceived from the simulation study were fare enough on both the side nodes of the proposed design. Categorically, the circuit can be aimed to work in lieu of a filter transceiver. The consistency of the circuit was analyzed by the nodal analysis. Whereas the working performance was enormously analyzed and evaluated during the simulation analysis. The proposed design was simulated in HSPICE tool to exhibit and exploit the delivery, using the 45[Formula: see text]nm predictive technology model (PTM) parameters, with [Formula: see text][Formula: see text]V rail to rail voltages. Maximum power consumption of the circuit is around 138.5[Formula: see text][Formula: see text]W. Finally, the design was also implemented in Cadence Virtuoso using 40[Formula: see text]nm SMIC parameters.