A 1.8 V 115.52 dB Third-Order Discrete-Time Sigma-Delta Modulator Using Nested Chopper Technology

Abstract

A Sigma-Delta modulator (SDM) realized with a fully differential third-order single-loop cascaded integrator feedforward (CIFF) architecture is proposed. A pair of low-frequency chopper switches are nested outside the chopper amplifier to further reduce the residual offset voltage. To reduce the power consumption and ensure linearity, a high-speed dynamic comparator is also used to implement a one-bit quantizer. The proposed architecture and the corresponding functionality are first simulated in MATLAB Simulink at the behavioral level. The results show that the designed modulator has an SNDR of 124.9[Formula: see text]dB corresponding to an ENOB of 20.46 bits at a clock frequency of 256[Formula: see text]kHz and 312.5[Formula: see text]Hz input with a differential-mode voltage of 700[Formula: see text]mV sinusoidal waveform. Based on SMIC 180[Formula: see text]nm/1.8[Formula: see text]V standard CMOS process on the Cadence platform, the subcircuit-level simulation is also performed, while the result shows that the proposed modulator can effectively achieve 115.52[Formula: see text]dB SNDR, 18.90-bit ENOB, and 8.40[Formula: see text]mW power consumption, which correspond to FoM[Formula: see text] and FoM[Formula: see text] of 0.067[Formula: see text]pJ/step and 163.27[Formula: see text]dB, respectively. The proposed modulator shows a significant advantage to be applied for high-precision analog-to-digital conversion applications such as high-quality equipment for audio, ECG and EEG signal sensing.