CODE SIZE REDUCTION FOR ARRAY INTENSIVE APPLICATIONS ON DIGITAL SIGNAL PROCESSORS

Abstract

Optimizing the code size for applications that run on a digital signal processors (DSPs) is a crucial step in generating high-quality and efficient code. Most modern DSP provide multiple address registers and dedicated address generation units that provide address generation in parallel to instruction execution. There is no address computation overhead if the next address is within the auto-modify range of the address register. Many DSP algorithms have an iterative pattern of references to array elements within loops. Thus, a careful assignment of array references to address registers (called the address register allocation or ARA problem) reduces the number of explicit address arithmetic instructions as well as the execution cycles. In this paper, we present an optimal integer linear programming formulation for the address register allocation problem which incorporates code restructuring techniques. In addition, we have developed a Genetic Algorithm solution for the ARA problem that allows us to get near-optimal solutions in a reasonable amount of time for large embedded applications. Results on several benchmarks show the effectiveness of our techniques compared to other techniques in the literature.