Erratum: High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic-Reference-Cited by-同舟云学术

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Erratum: High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic

Published:2022-10-29 Issue:18 Volume:31 Page:
ISSN:0218-1266
Container-title:Journal of Circuits, Systems and Computers
language:en
Short-container-title:J CIRCUIT SYST COMP

Author:

Khairnar Avadhoot¹,Chauhan Bhavuk²,Sharma Geetanjali³⁴,Joshi Amit M.⁵

Affiliation:

1. Department of Electrical Engineering, Indian Institute of Technology, Bombay, India

2. Department of Electronics and Communication Engineering, National Institute of Technology, Warangal, India

3. Department of Electronics and Communication Engineering, Malviya National Institute of Technology, Jaipur, India

4. Maharaja Surajmal Institute of Technology, New Delhi, India

5. Department of Electronics and Communication Engineering, Malaviya National Institute of Technology, Jaipur, India

Publisher

World Scientific Pub Co Pte Ltd

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Media Technology

Link

https://www.worldscientific.com/doi/pdf/10.1142/S0218126622920013

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