Design of Low Voltage Low Power DC–DC Converters Using Adiabatic Technique

Abstract

In this paper two low voltage, low power DC–DC converter circuits have been designed with input voltages as low as 290[Formula: see text]mV to 500[Formula: see text]mV. Adiabatic technique has been used to reduce power consumption and increase the efficiency of the charge pump of the converters. Boost converter circuits are simulated and the efficiency and power consumption are improved using adiabatic technique. Optimum capacitor bank and rise time–fall time values have been obtained for the adiabatic circuits. Power consumption for the doubler circuit with 310[Formula: see text]mV input decreases by 67% using adiabatic technique and 0.18[Formula: see text][Formula: see text]m CMOS technology parameters.