A Developed Two-Leg Ladder Multilevel Converter Structure

Abstract

The applications of multilevel converters (MCs) in industry have been increased because of their advantages such as high quality output waveform and lower harmonic distortions. This paper proposes an improved two-leg ladder topology for MC. For generating all levels at output voltage waveform, two methods are investigated for selecting the values of dc sources. The suggested structure generates a large number of levels at output voltage waveform with the least number of power electronic components such as insulated gate bipolar transistors, gate driver circuits, dc voltage sources and anti-parallel diodes in comparison with other similar topologies. Also, the magnitude of blocked voltage by switches is low. Power losses analysis on the proposed topology is provided. It is shown that the number of on-state switches in the presented structure is less than other similar topologies, which causes the voltage drop and power losses of proposed topology to be reduced. To show the merits of the proposed structure, comparison results are provided with other structures. To validate the analytical results of proposed topology, an experimental work for a 9-level converter and the simulation results for a 25-level converter are provided. PSCAD/EMTDC software is used for simulation works.