Power Attack Vulnerability Assessment of Circuit-Level PRESENT Encryption IP Using Artificial Intelligence Mechanisms

Abstract

Artificial Intelligence (AI) schemes eliminate the need for intellectual human knowledge of crypto algorithms to facilitate side-channel attacks on security implementations. Side channel attack analysis for circuit-level hardware (VLSI) implementations of symmetric-key block ciphers through artificial machine models are yet to be addressed. The proposed design of block cipher architecture, which is the implementation under attack features, secure adiabatic logic style the Charge Balancing Symmetric Pre-resolve Adiabatic Logic (CBSPAL). This style exhibits uniform power consumption through its inherent circuit arrangement, which makes it robust toward side-channel power attacks. This paper considers several Multilayer Perceptron (MLP) architectures to mount non-profiled side-channel attacks on round 1- PRESENT circuit-level implementation. Supervised learning of the MLP models through training with power waveforms employs binary LSB labeling. An attack on the custom dataset with 50,000 supply power traces collected from the CBSPAL implementation fails to retrieve secret information in any of the 8 bytes. The traditional Correlation Power Attack (CPA) was also not thriving with the proposed implementation. Comparison is made through a similar attack approach on benchmark AES (ASCAD dataset), which distinguishes the secret information throughout all the parameters of interest: normalized accuracy, normalized NMM accuracy and rank plots on byte 3.