A LOW OFFSET HIGH SPEED COMPARATOR FOR PIPELINE ADC-Reference-Cited by-同舟云学术

A LOW OFFSET HIGH SPEED COMPARATOR FOR PIPELINE ADC

Published:2013-04 Issue:04 Volume:22 Page:1350018
ISSN:0218-1266
Container-title:Journal of Circuits, Systems and Computers
language:en
Short-container-title:J CIRCUIT SYST COMP

Author:

ZHU ZHANGMING¹,WU HONGBING¹,YU GUANGWEN¹,LI YANHONG¹,LIU LIANXI¹,YANG YINTANG¹

Affiliation:

1. School of Microelectronics, Xidian University, 2 Taibai Road, Xi'an 710071, P. R. China

Abstract

A low offset and high speed preamplifier latch comparator is proposed for high-speed pipeline analog-to-digital converters (ADCs). In order to realize low offset, both offset cancellation techniques and kickback noise reduction techniques are adopted. Based on TSMC 0.18 μm 3.3 V CMOS process, Monte Carlo simulation shows that the comparator has a low offset voltage 1.1806 mV at 1 sigma at 125 MHz, with a power dissipation of 413.48 μW.

Publisher

World Scientific Pub Co Pte Lt

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

Link

https://www.worldscientific.com/doi/pdf/10.1142/S0218126613500187

Reference4 articles.

1. Design techniques for high-speed, high-resolution comparators

2. Low-power and low-offset comparator using latch load

3. A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM

4. Device mismatch and tradeoffs in the design of analog circuits

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