Affiliation:
1. Department of Computer Science and Engineering, Yuan Ze University, 135 Yuan-Tung Road, Chung-Li 320, Taiwan
Abstract
Multiple project wafers (MPWs) containing different chip designs from many customers serves as an important vehicle for gaining access to advanced semiconductor process technology for prototyping innovative designs or low-volume production. In this paper, a comprehensive study on the methods for determining dicing plans for MPW was carried out. Dicing plans can be used to determine the number of MPWs needed to be fabricated before chip fabrication and employed to saw the wafers after fabrication. Several methods based on integer linear programming formulation and a heuristic based on simulated annealing was proposed. Through conducting experiments with industrial test cases, these proposed methods can achieve up to 50% wafer reduction in some cases and on average 18% and 38% reduction for low- and high-volume production, respectively. This study makes a contribution to MPW dicing and is also instrumental in developing better reticle floorplanning methods.
Publisher
World Scientific Pub Co Pte Lt
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture