AREA-EFFICIENT DIGIT SERIAL–SERIAL TWO'S COMPLEMENT MULTIPLIER

Abstract

Although parallel multipliers are optimal for speed, they occupy considerable chip area. For applications with lengthy operands as cryptography, the required area grows further. On the other hand, digit multipliers reduce chip area at the expense of the number of cycles required to complete the multiplication. In such multipliers, one-or-both inputs are received serially one digit per cycle. Digit multiplier designs are flexible with respect to the digit width enabling designers to select the most suitable compromise between area and cycle count for the application under consideration. This paper proposes a new digit serial–serial multiplier that is more area efficient compared to other functionally-similar multipliers. First, we propose a new unsigned digit serial–serial multiplier that is area efficient. The multiplier has the ability to handle unequal-width operands. That is, one operand can be of dynamic width (unlimited digit count) and the other operand is of fixed width. Moreover, with a small modification, the multiplier can operate on two's complement operands. Then, the design is extended to support bit-level pipelining: the critical path of the multiplier pipeline stage is independent of the operand width and the digit width. Simulation results show that the proposed multiplier reduces the area over similar multipliers by up to 28% and reduces power by up to 31%.