Mixed-Voltage I/O Buffer Using NMOS Blocking Considering Gate Oxide Reliability-Reference-Cited by-同舟云学术

Mixed-Voltage I/O Buffer Using NMOS Blocking Considering Gate Oxide Reliability

Published:2022-04-18 Issue:11 Volume:31 Page:
ISSN:0218-1266
Container-title:Journal of Circuits, Systems and Computers
language:en
Short-container-title:J CIRCUIT SYST COMP

Author:

Nedalgi Dharmaray¹,Siddamal Saroja V.²^ORCID

Affiliation:

1. Intel Technology India Private Limited, NO 23-56 P, Outer Ring Road (SRR4), Devarabeesanahalli, Varthur Hobli, Bangalore 560103, India

2. Department of Electronics and Communication, KLE Technological University, Hubli, India

Abstract

This paper presents a [Formula: see text] tolerant I/O buffer with low voltage (VDD) devices. A novel bootstrap circuit for mixed voltage I/O buffer is proposed to solve the unwanted leakage paths and gate oxide reliability issues. The proposed circuit is designed using 1.8[Formula: see text]V thick gate devices in 22-nm FinFET technology with 1.8[Formula: see text]V signaling and tolerant to 3.3[Formula: see text]V. The structure can be used in any CMOS technology for [Formula: see text] tolerant I/O buffer.

Publisher

World Scientific Pub Co Pte Ltd

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

Link

https://www.worldscientific.com/doi/pdf/10.1142/S0218126622502024

Reference11 articles.

1. 5.5-V I/O in a 2.5-V 0.25-μm CMOS technology

2. High-voltage-tolerant I/O buffers with low-voltage CMOS process

3. Design of Mixed-Voltage I/O Buffer by Using NMOS-Blocking Technique

4. A 3/5 V compatible I/O buffer

5. Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-μm CMOS technology