High-Performance Multi-Stage CMOS OTA Design Using Differential Block As Compensation Network

Abstract

This work presents an effective and straightforward frequency compensation scheme in CMOS three-stage amplifiers. Using a differential block in the compensation network, the proposed circuit shows independent and large first dominant pole regarding the DC gain path. The presented three-stage architecture is frequency-compensated just by a single Miller capacitor. Mathematical analysis is presented along with ample simulations that are performed using TSMC 0.18-[Formula: see text]m CMOS technology. According to the results, the proposed circuit shows DC gain equal to 118[Formula: see text]dB, GBW equal to 466[Formula: see text]MHz, PM equal to 74.3∘ and 1.2[Formula: see text]mW as power consumption, respectively. The high values of DC gain and GBW make the proposed amplifier appropriate for more speedy operations such as high-speed modulators and data converters.