A CMOS Low-Voltage Super Follower Using Quasi-Floating Gate Techniques-Reference-Cited by-同舟云学术

A CMOS Low-Voltage Super Follower Using Quasi-Floating Gate Techniques

Published:2018-03-26 Issue:07 Volume:27 Page:1850111
ISSN:0218-1266
Container-title:Journal of Circuits, Systems and Computers
language:en
Short-container-title:J CIRCUIT SYST COMP

Author:

Ocampo-Hidalgo J. J.¹,Alducín-Castillo J.¹,Vázquez-Álvarez I.¹,Oliva-Moreno L. N.²,Molinar-Solís J. E.³

Affiliation:

1. Departamento de Electrónica, Universidad Autónoma Metropolitana Azcapotzalco, Sn. Pablo 180, Col. Reynosa Tamaulipas, Mexico City 02200, México

2. Instituto Politécnico Nacional, Av. Juan de Dios Bátiz esq., Av. Miguel Othón de Mendizábal, Col. Lindavista, Mexico City 07738, México

3. Instituto Tecnológico de Ciudad Guzmán, Av. Tecnológico 100, Ciudad Guzmán, Jalisco 49100, México

Abstract

A quasi-floating gate (QFG) “super-follower” is presented. The high resistance used by the QFG transistor is constructed by two diodes connected back-to-back, leading to a simple-, temperature-stable- and small-area solution. Expressions for the behavior of the follower are introduced and verified by circuit simulations in LTSPICE using 0.5[Formula: see text][Formula: see text]m CMOS process models, which show an improved performance of the proposed circuit with respect to the original super-follower. To prove the principle, a test cell was fabricated in the same 0.5[Formula: see text][Formula: see text]m CMOS technology and characterized. Measurement results show a gain-bandwidth product of 10[Formula: see text]MHz and power consumption of 120[Formula: see text][Formula: see text]W with a 1.5[Formula: see text]V single supply.

Publisher

World Scientific Pub Co Pte Lt

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

Link

https://www.worldscientific.com/doi/pdf/10.1142/S0218126618501116

Reference23 articles.

1. A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18-$\mu{\rm m}$ CMOS for Medical Implant Devices

2. A 0.5-V power-efficient low-noise CMOS instrumentation amplifier for wireless biosensor

3. CMOS analog integrated circuits based on weak inversion operations

4. A 0.45 V, Nano-Watt 0.033% Line Sensitivity MOSFET-Only Sub-Threshold Voltage Reference With no Amplifiers

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