High-Performance Hardware Implementation of the KATAN Lightweight Cryptographic Cipher

Abstract

Lightweight cryptography has been proposed recently as an attractive solution to provide security for the ever-growing number of IoT resource-constrained devices. Many of the proposed lightweight cryptographic ciphers have been implemented in software. However, for practical embedded IoT applications, hardware implementations are preferred because they have small silicon area and low-power consumption. In this paper, we present a transistor-level hardware implementation of the well-known KATAN lightweight cipher. This cipher has been chosen due to its operational simplicity and high levels of security. Moreover, the structure of the KATAN cipher lends itself naturally for transistor-level hardware implementation. The design has been implemented at the transistor level using the advanced new 28-nm CMOS technology which facilitates optimized designs for the resource-constrained IoT devices. The proposed VLSI KATAN encryption and decryption circuits have been designed and simulated using the Synopsys Custom Designer Tool using 28-nm technology, 0.9 v supply voltage and a 1 GHz clock signal. The KATAN encryption circuit has 312 GE (Gate Equivalent) without key and irregular update registers, and 1081 GE for the overall design, and the decryption circuit has 390 GE without memory registers and 6867 GE for the overall design.