COMBINING THE FOLDING AND TESTING FOR PROGRAMMABLE LOGIC ARRAYS
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Published:1994-09
Issue:03
Volume:04
Page:305-317
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ISSN:0218-1266
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Container-title:Journal of Circuits, Systems and Computers
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language:en
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Short-container-title:J CIRCUIT SYST COMP
Author:
WEI KAI-CHENG1,
LIU BIN-DA1
Affiliation:
1. Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan 70101, R.O.C
Abstract
Different from the previous techniques which treated the folding and testing for PLAs as separate problems, this paper presents a new approach to combine the bipartite folding and testing for PLA’s in the same procedure. Fewer silicon area than other existing comparable techniques is required to make the PLA testable. Experimental results show that this technique can reduce chip area, test length, test storage and time complexity.
Publisher
World Scientific Pub Co Pte Lt
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture